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hn58v65a series hn58v66a series 64 k eeprom (8-kword 8-bit) ready/ busy function, res function (hn58v66a) ade-203-539b (z) rev. 2.0 nov. 1997 description the hitachi hn58v65a series and hn58v66a series are a electrically erasable and programmable eeprom? organized as 8192-word 8-bit. they have realized high speed, low power consumption and high relisbility by employing advanced mnos memory technology and cmos process and circuitry technology. they also have a 64-byte page programming function to make their write operations faster. features single supply: 2.7 to 5.5 v access time: ? 100 ns (max) at 2.7 v v cc < 4.5 v ? 70 ns (max) at 4.5 v v cc 5.5 v power dissipation: ? active: 20 mw/mhz (typ) ? standby: 110 m w (max) on-chip latches: address, data, ce , oe , we automatic byte write: 10 ms (max) automatic page write (64 bytes): 10 ms (max) ready/ busy data polling and toggle bit data protection circuit on power on/off conforms to jedec byte-wide standard reliable cmos with mnos cell technology
hn58v65a series, hn58v66a series features (cont) 10 5 erase/write cycles (in page mode) 10 years data retention software data protection write protection by res pin (only the hn58v66a series) industrial versions (temperatur range: ?0 to 85?c and ?0 to 85?c) are also available. ordering information access time type no. 2.7 v v cc < 4.5 v 4.5 v v cc 5.5 v package hn58v65ap-10 100 ns 70 ns 600 mil 28-pin plastic dip (dp-28) hn58v66ap-10 100 ns 70 ns hn58v65afp-10 100 ns 70 ns 400 mil 28-pin plastic sop (fp-28d) HN58V66AFP-10 100 ns 70 ns hn58v65at-10 100 ns 70 ns 28-pin plastic tsop(tfp-28db) hn58v66at-10 100 ns 70 ns pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we nc a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 rdy/ busy a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss (top view) hn58v65ap series hn58v65afp series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we res a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 rdy/ busy a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss (top view) hn58v66ap series hn58v66afp series
hn58v65a series, hn58v66a series pin arrangement (cont) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a2 a1 a0 i/o0 i/o1 i/o2 v i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 ss a3 a4 a5 a6 a7 a12 rdy/ busy v we nc a8 a9 a11 oe cc (top view) hn58v65at series 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a2 a1 a0 i/o0 i/o1 i/o2 v i/o3 i/o4 i/o5 i/o6 i/o7 ce a10 ss a3 a4 a5 a6 a7 a12 rdy/ busy v we res a8 a9 a11 oe cc (top view) hn58v66at series 15 16 17 18 19 20 21 22 23 24 25 26 27 28
hn58v65a series, hn58v66a series pin description pin name function a0 to a12 address input i/o0 to i/o7 data input/output oe output enable ce chip enable we write enable v cc power supply v ss ground rdy/ busy ready busy res * 1 reset nc no connection notes: 1. this function is supported by only the hn58v66a series. block diagram notes: this function is supported by only the hn58v66a series. v v oe ce a5 a0 a6 a12 we cc ss i/o0 i/o7 high voltage generator control logic and timing y decoder x decoder address buffer and latch i/o buffer and input latch y gating memory array data latch res rdy/ busy res * 1 * 1 to to to
hn58v65a series, hn58v66a series operation table operation ce oe we res * 3 rdy/ busy i/o read v il v il v ih v h * 1 high-z dout standby v ih * 2 high-z high-z write v il v ih v il v h high-z to v ol din deselect v il v ih v ih v h high-z high-z write inhibit v ih v il data polling v il v il v ih v h v ol dout (i/o7) program reset v il high-z high-z notes: 1. refer to the recommended dc operating conditions. 2. : don? care 3. this function supported by only the hn58v66a series. absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ?.6 to +7.0 v input voltage relative to v ss vin ?.5* 1 to +7.0* 3 v operating temperature range * 2 topr 0 to +70 ?c storage temperature range tstg ?5 to +125 ?c notes: 1. vin min : ?.0 v for pulse width 50 ns. 2. including electrical characteristics and data retention. 3. should not exceed v cc + 1 v.
hn58v65a series, hn58v66a series recommended dc operating conditions parameter symbol min typ max unit supply voltage v cc 2.7 5.5 v v ss 000v input voltage v il ?.3* 1 0.6* 5 v v ih 1.9* 2 ? cc + 0.3* 3 v v h * 4 v cc ?0.5 v cc + 1.0 v operating temperature topr 0 70 ?c notes: 1. v il min: ?.0 v for pulse width 50 ns. 2. v ih = 2.2 v for v cc = 3.6 to 5.5 v. 3. v ih max: v cc + 1.0 v for pulse width 50 ns. 4. this function is supported by only the hn58v66a series. 5. v il = 0.8 v for v cc = 3.6 v to 5.5 v dc characteristics (ta = 0 to + 70?c, v cc = 2.7 to 5.5 v) parameter symbol min typ max unit test conditions input leakage current i li 2* 1 m a vin = 0 v to v cc output leakage current i lo 2 m a vout = 0 v to v cc standby v cc curren i cc1 1 to 2 5 m a ce = v cc ?0.3 v to v cc + 1.0 v i cc2 1ma ce = v ih operating v cc current i cc3 6 ma iout = 0 ma, duty = 100%, cycle = 1 m s at v cc = 3.6 v 8 ma iout = 0 ma, duty = 100%, cycle = 1 m s at v cc = 5.5 v 12 ma iout = 0 ma, duty = 100%, cycle = 100 ns at v cc = 3.6 v 25 ma iout = 0 ma, duty = 100%, cycle = 70 ns at v cc = 5.5 v output low voltage v ol 0.4 v i ol = 2.1 ma output high voltage v oh v cc 0.8 v i oh = ?00 m a note: 1. i li on res : 100 m a max (only the hn58v66a series) capacitance (ta = 25?c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance cin* 1 6 pf vin = 0 v output capacitance cout* 1 12 pf vout = 0 v note: 1. this parameter is sampled and not 100% tested.
hn58v65a series, hn58v66a series ac characteristics (ta = 0 to + 70?c, v cc = 2.7 to 5.5 v) test conditions input pulse levels : 0.4 v to 2.4 v (v cc = 2.7 to 3.6 v), 0.4 v to 3.0 v (v cc = 3.6 to 5.5 v) 0 v to v cc ( res pin* 2 ) input rise and fall time : 5 ns input timing reference levels : 0.8, 1.8 v output load : 1ttl gate +100 pf output reference levels : 1.5 v, 1.5 v read cycle 1 (v cc = 2.7 to 4.5 v) hn58v65a/hn58v66a -10 parameter symbol min max unit test conditions address to output delay t acc 100 ns ce = oe = v il , we = v ih ce to output delay t ce 100 ns oe = v il , we = v ih oe to output delay t oe 10 50 ns ce = v il , we = v ih address to output hold t oh 0ns ce = oe = v il , we = v ih oe ( ce ) high to output float* 1 t df 040ns ce = v il , we = v ih res low to output float* 1, 2 t dfr 0 350 ns ce = oe = v il , we = v ih res to output delay* 2 t rr 0 450 ns ce = oe = v il , we = v ih
hn58v65a series, hn58v66a series write cycle 1 (v cc = 2.7 to 4.5 v) parameter symbol min* 3 typ max unit test conditions address setup time t as 0 ns address hold time t ah 50ns ce to write setup time ( we controlled) t cs 0 ns ce hold time ( we controlled) t ch 0 ns we to write setup time ( ce controlled) t ws 0 ns we hold time ( ce controlled) t wh 0 ns oe to write setup time t oes 0 ns oe hold time t oeh 0 ns data setup time t ds 50ns data hold time t dh 0 ns we pulse width ( we controlled) t wp 200 ns ce pulse width ( ce controlled) t cw 200 ns data latch time t dl 100 ns byte load cycle t blc 0.3 30 m s byte load window t bl 100 m s write cycle time t wc 10* 4 ms time to device busy t db 120 ns write start time t dw 0* 5 ns reset protect time* 2 t rp 100 m s reset high time* 2, 6 t res 1 m s notes: 1. t df and t dfr are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. this function is supported by only the hn58v66a series. 3. use this device in longer cycle than this value. 4. t wc must be longer than this value unless polling techniques or rdy/ busy are used. this device automatically completes the internal write operation within this value. 5. next read or write operation can be initiated after t dw if polling techniques or rdy/ busy are used. 6. this parameter is sampled and not 100% tested. 7. a6 through a12 are page addresses and these addresses are latched at the first falling edge of we . 8. a6 through a12 are page addresses and these addresses are latched at the first falling edge of ce . 9. see ac read characteristics.
hn58v65a series, hn58v66a series read cycle 2 (v cc = 4.5 to 5.5 v) hn58v65a/hn58v66a -10 parameter symbol min max unit test conditions address to output delay t acc ?0ns ce = oe = v il , we = v ih ce to output delay t ce ?0ns oe = v il , we = v ih oe to output delay t oe 10 40 ns ce = v il , we = v ih address to output hold t oh 0ns ce = oe = v il , we = v ih oe ( ce ) high to output float* 1 t df 030ns ce = v il , we = v ih res low to output float* 1, 2 t dfr 0 350 ns ce = oe = v il , we = v ih res to output delay* 2 t rr 0 450 ns ce = oe = v il , we = v ih
hn58v65a series, hn58v66a series write cycle 2 (v cc = 4.5 to 5.5 v) parameter symbol min* 3 typ max unit test conditions address setup time t as 0 ns address hold time t ah 50ns ce to write setup time ( we controlled) t cs 0 ns ce hold time ( we controlled) t ch 0 ns we to write setup time ( ce controlled) t ws 0 ns we hold time ( ce controlled) t wh 0 ns oe to write setup time t oes 0 ns oe hold time t oeh 0 ns data setup time t ds 50ns data hold time t dh 0 ns we pulse width ( we controlled) t wp 100 ns ce pulse width ( ce controlled) t cw 100 ns data latch time t dl 50ns byte load cycle t blc 0.2 30 m s byte load window t bl 100 m s write cycle time t wc 10* 4 ms time to device busy t db 120 ns write start time t dw 0* 5 ns reset protect time* 2 t rp 100 m s reset high time* 2, 6 t res 1 m s notes: 1. t df and t dfr are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. this function is supported by only the hn58v66a series. 3. use this device in longer cycle than this value. 4. t wc must be longer than this value unless polling techniques or rdy/ busy are used. this device automatically completes the internal write operation within this value. 5. next read or write operation can be initiated after t dw if polling techniques or rdy/ busy are used. 6. this parameter is sampled and not 100% tested. 7. a6 through a12 are page addresses and these addresses are latched at the first falling edge of we . 8. a6 through a12 are page addresses and these addresses are latched at the first falling edge of ce . 9. see ac read characteristics.
hn58v65a series, hn58v66a series read timing waveform address ce oe we data out high data out valid t acc t ce t oe t oh t df t rr t dfr res * 2
hn58v65a series, hn58v66a series byte write timing waveform(1) ( we controlled) address ce we oe din rdy/ busy t wc t ch t ah t cs t as t wp t oeh t bl t oes t ds t dh t db t rp res * 2 v cc t res high-z high-z t dw
hn58v65a series, hn58v66a series byte write timing waveform(2) ( ce controlled) address ce we oe din rdy/ busy t wc t ah t ws t as t oeh t wh t oes t ds t dh t db t rp res * 2 v cc t cw t bl t dw t res high-z high-z
hn58v65a series, hn58v66a series page write timing waveform(1) ( we controlled) address a0 to a12 we ce oe din rdy/ busy t as t ah t bl t wc t oeh t dh t db t oes t rp t res res * 2 v cc t ch t cs t wp t dl t blc t ds t dw high-z high-z *7
hn58v65a series, hn58v66a series page write timing waveform(2) ( ce controlled) address a0 to a12 we ce oe din rdy/ busy t as t ah t bl t wc t oeh t dh t db t oes t rp t res res * 2 v cc t wh t ws t cw t dl t blc t ds t dw high-z high-z *8
hn58v65a series, hn58v66a series data polling timing waveform t ce t oeh t wc t dw t oes address ce we oe i/o7 t oe din x an an dout x dout x *9 *9 an
hn58v65a series, hn58v66a series toggle bit this device provide another function to determine the internal programming cycle. if the eeprom is set to read mode during the internal programming cycle, i/o6 will charge from ??to ??(toggling) for each read. when the internal programming cycle is finished, toggling of i/o6 will stop and the device can be accessible for next read or program. toggle bit waveform notes: 1. i/o6 begining state is ?? 2. i/o6 ending state will vary. 3. see ac read characteristics. 4. any address location can be used, but the address must be fixed. we t oes oe ce dout i/o6 dout dout dout next mode t oe t ce t dw t wc t oeh *1 *2 *2 address *3 *3 *4 din
hn58v65a series, hn58v66a series software data protection timing waveform(1) (in protection mode) v ce we address data 1555 aa 0aaa 55 1555 a0 t blc t wc cc write address write data software data protection timing waveform(2) (in non-protection mode) v ce we address data t wc cc normal active mode 1555 aa 0aaa 55 1555 80 1555 aa 0aaa 55 1555 20
hn58v65a series, hn58v66a series functional description automatic page write page-mode write feature allows 1 to 64 bytes of data to be written into the eeprom in a single write cycle. following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. each additional byte load cycle must be started within 30 m s from the preceding falling edge of we or ce . when ce or we is kept high for 100 m s after data input, the eeprom enters write mode automatically and the input data are written into the eeprom. data polling data polling indicates the status that the eeprom is in a write cycle or not. if eeprom is set to read mode during a write cycle, an inversion of the last byte of data outputs from i/o7 to indicate that the eeprom is performing a write operation. rdy/ busy signal rdy/ b us y signal also allows status of the eeprom to be determined. the rdy/ busy signal has high impedance except in write cycle and is lowered to v ol after the first write signal. at the end of a write cycle, the rdy/ busy signal changes state to high impedance. res signal (only the hn58v66a series) when res is low, the eeprom cannot be read or programmed. therefore, data can be protected by keeping res low when v cc is switched. res should be high during read and programming because it doesn? provide a latch function. v program inhibit cc res program inhibit read inhibit read inhibit
hn58v65a series, hn58v66a series we , ce pin operation during a write cycle, addresses are latched by the falling edge of we or ce , and data is latched by the rising edge of we or ce . write/erase endurance and data retention time the endurance is 10 5 cycles in case of the page programming and 10 4 cycles in case of the byte programming (1% cumulative failure rate). the data retention time is more than 10 years when a device is page-programmed less than 10 4 cycles. data protection 1. data protection against noise on control pins ( ce , oe , we ) during operation during readout or standby, noise on the control pins may act as a trigger and turn the eeprom to programming mode by mistake. to prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 15 ns or less. be careful not to allow noise of a width of more than 15 ns on the control pins. we ce oe v 0 v v 0 v 15 ns max ih ih
hn58v65a series, hn58v66a series 2. data protection at v cc on/off when v cc is turned on or off, noise on the control pins generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to program mode by mistake. to prevent this unintentional programming, the eeprom must be kept in an unprogrammable state while the cpu is in an unstable state. note: the eeprom shoud be kept in unprogrammable state during v cc on/off by using cpu reset signal. v cc cpu reset unprogrammable unprogrammable * * (1) protection by ce , oe , we to realize the unprogrammable state, the input level of control pins must be held as shown in the table below. ce v cc oe v ss we v cc : don? care. v cc : pull-up to v cc level. v ss : pull-down to v ss level.
hn58v65a series, hn58v66a series (2) protection by res (only the hn58v66a series) the unprogrammable state can be realized by that the cpu? reset signal inputs directly to the eeprom? res pin. res should be kept v ss level during v cc on/off. the eeprom breaks off programming operation when res becomes low, programming operation doesn? finish correctly in case that res falls low during programming operation. res should be kept high for 10 ms after the last data input. v cc res we or ce 100 s min 10 ms min 1 s min program inhibit program inhibit
hn58v65a series, hn58v66a series 3. software data protection to prevent unintentional programming caused by noise generated by external circuits, this device has the software data protection function. in software data protection mode, 3 bytes of data must be input before write data as follows. and these bytes can switch the non-protection mode to the protection mode. sdp is enabled if only the 3 bytes code is input. data aa 55 a0 write data } address 1555 0aaa 1555 write address normal data input software data protection mode can be cancelled by inputting the following 6 bytes. after that, this device turns to the non-protection mode and can write data normally. but when the data is input in the cancelling cycle, the data cannot be written. data aa 55 80 aa 55 20 address 1555 0aaa 1555 1555 0aaa 1555 the software data protection is not enabled at the shipment. note: there are some differences between hitachi? and other company? for enable/disable sequence of software data protection. if there are any questions , please contact with hitachi sales offices.
hn58v65a series, hn58v66a series package dimensions hn58v65ap series hn58v66ap series (dp-28) 0.51 min 2.54 min 0.25 + 0.11 ?0.05 2.54 0.25 0.48 0.10 0 ?15 15.24 1.2 35.6 36.5 max 13.4 14.6 max 1 14 15 28 5.70 max 1.9 max hitachi code jedec code eiaj code weight (reference value) dp-28 sc-510-28e 4.6 g unit: mm
hn58v65a series, hn58v66a series package dimensions (cont) hn58v65afp series hn58v66afp series (fp-28d) 0 ?8 0.17 0.05 1.0 0.2 0.20 0.10 2.50 max 8.4 18.3 18.8 max 1.12 max 28 15 1 14 11.8 0.3 1.7 0.20 0.15 m 1.27 0.40 0.08 0.38 0.06 0.15 0.04 hitachi code jedec code eiaj code weight (reference value) fp-28d mo-059-ac 0.7 g unit: mm dimension including the plating thickness base material dimension
hn58v65a series, hn58v66a series package dimensions (cont) hn58v65at series hn58v66at series (tfp-28db) 0.10 m 0.55 8.00 0.22 0.08 13.40 0.30 0.17 0.05 0.13 1.20 max 11.80 0 ?5 28 1 14 15 8.20 max 0.10 +0.07 ?.08 0.50 0.10 0.80 0.45 max hitachi code jedec code eiaj code weight (reference value) tfp-28db 0.23 g 0.20 0.06 0.15 0.04 unit: mm dimension including the plating thickness base material dimension
hn58v65a series, hn58v66a series when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachi? permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user? unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi? semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachi? products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi? sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachi? products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071

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